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US 2017/0285991 A1Published application
N plane to 2n plane interface in a solid state drive (ssd) architecture
AssigneeIntel Corporation
InventorsAliasgar S. MADRASWALA, Xin GUO, Joel T. JORGENSEN
Life of this patent
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Abstract
A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.
Claims21
A solid state drive comprising:
- a nonvolatile storage device including a number 2N of planes of memory cells;
- and
- a controller including a 1N plane hardware interface coupled to the nonvolatile storage device;
- wherein a data access transaction between the controller and the nonvolatile storage device includes first and second consecutive 1N plane command sequences interpreted as a single 2N plane command sequence.
1 more element
A computing system, comprising:
- a multicore processor to execute instructions;
- a volatile memory device to store data to be executed by the processor;
- and
- a solid state drive coupled to the processor and the volatile memory device, the solid state drive including
- a nonvolatile storage device including a number 2N of planes of memory cells;
- and
- a controller including a 1N plane hardware interface coupled to the nonvolatile storage device;
- wherein a data access transaction between the controller and the nonvolatile storage device includes first and second consecutive 1N plane command sequences interpreted as a single 2N plane command sequence.
5 more elements
A method for storing data, comprising:
- sending a first data access transaction from a controller having a 1N plane hardware interface to a nonvolatile storage device having 2N planes of memory cells, wherein the first data access transaction to address 1N planes of memory cells;
- and
- sending a consecutive second data access transaction to address 1N planes from the controller to the nonvolatile storage device;
- wherein the nonvolatile storage device to interpret the consecutive 1N plane data access transactions as a 2N plane data access transaction.
1 more element
Dependencies are inferred from the claim text.