Hardware apparatuses and methods for memory compression and decompression
AssigneeIntel Corporation
InventorsKirk S. Yap, Vinodh Gopal, James D. Guilford, Sean M. Gulley
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AssigneeIntel Corporation
InventorsKirk S. Yap, Vinodh Gopal, James D. Guilford, Sean M. Gulley
Estimating the term…
Methods and apparatuses relating to memory compression and decompression are described. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match.
A memory controller comprising:
A method comprising:
A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
Dependencies are inferred from the claim text.