Memory copy instructions, processors, methods, and systems

A processor comprising:

• a decode unit to decode a memory copy instruction that is to indicate a source memory operand, to indicate a destination memory operand, and to indicate an amount of data to be copied from the source memory operand to the destination memory operand;
• and
• an execution unit coupled with the decode unit, the execution unit, in response to the memory copy instruction, to:
• determine a copy direction to use to start to copy data from the source memory operand to the destination memory operand without using an indication of a copy direction generated outside of performance of the memory copy instruction.

A method performed by a processor comprising:

• receiving a memory copy instruction at the processor, the memory copy instruction indicating a start of a source memory operand, indicating a start of a destination memory operand, and indicating an architecturally visible storage location that stores an initial amount of data to be copied from the source memory operand to the destination memory operand;
• determining, in response to the memory copy instruction, that the source and destination memory operands overlap;
• copying, in response to the memory copy instruction, a first portion of data from the source memory operand to the destination memory operand, in a descending copy direction, before an interruption;
• and
• in response to the interruption, and since the first portion of data was copied in the descending copy direction, storing a remaining amount of data to be copied, which represents the initial amount of data less the first portion of data, in the architecturally visible storage location, without indicating a different start of the source memory operand, and without indicating a different start of the destination memory operand.

A computer system comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive a memory copy instruction that is to indicate a start of a source memory operand, is to indicate a start of a destination memory operand, and is to indicate an architecturally visible storage location that is to store an initial amount of data to be copied from the source memory operand to the destination memory operand, the processor, in response to the memory copy instruction, to copy a first portion of data from the source memory operand to the destination memory operand before an interruption, wherein the first portion of data is to be copied in a descending copy direction, and in response to the interruption, and when the first portion of data is to be copied in the descending copy direction, to store a remaining amount of data to be copied in the architecturally visible storage location, but not to indicate a different start of the source memory operand, and not to indicate a different start of the destination memory operand;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.