Multiple memory rank system and selection method thereof

A computer-readable storage medium having instructions stored thereon that, in response to execution by a processing device, causes the processing device to perform operations comprising:

• resetting at least one first memory device on a first rank and at least one second memory device on a second rank by encoding a reset signal in a first command/address signal and in a second command/address signal and transmitting the reset signal to the at least one first memory device and to the at least one second memory device;
• assigning a first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assigning a second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal by encoding an assignment signal in the second command/address signal and transmitting the assignment signal to the at least one first memory device and to the at least one second memory device;
• and
• selecting the first rank or the second rank by encoding a selection signal in the first command/address signal and transmitting the selection signal to the at least one first memory device and to the at least one second memory device.

A method comprising:

• resetting at least one first memory device on a first rank and at least one second memory device on a second rank by encoding a reset signal in a first command/address signal and in a second command/address signal and transmitting the reset signal to the at least one first memory device and to the at least one second memory device;
• assigning a first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assigning a second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal by encoding an assignment signal in the second command/address signal and transmitting the assignment signal to the at least one first memory device and to the at least one second memory device;
• and
• selecting the first rank or the second rank by encoding a selection signal in the first command/address signal and transmitting the selection signal to the at least one first memory device and to the at least one second memory device.

A system comprising:

• a first rank comprising at least one first memory device including a first input terminal and a second input terminal;
• a second rank comprising at least one second memory device including a first input terminal and a second input terminal;
• and
• a controller configured to:
• reset that at least one first memory device of the first rank and that at least one second memory device of the second rank based at least in part on a reset signal encoded in a first command/address signal and in a second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device;
• assign the first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assign the second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal based at least in part on an assignment signal encoded in the second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device;
• and
• select the first rank or the second rank based at least in part on a selection signal encoded in the first command/address signal and transmitted to the at least one first memory device and to the at least one second memory device.