Apparatus, System, And Method Of Logical Address Translation For Non-Volatile Storage Memory

A storage system communicatively coupled with a host system, the storage system comprising:

• an array of non-volatile memories;
• an internal volatile memory;
• multiple address translation tables each having multiple entries, wherein content in each entry comprises a non-volatile physical address portion, a volatile physical address portion, a valid flag, and a cache valid flag;
• and
• an internal processing unit communicatively coupled with the host system, and configured to:
• receive, from the host system, a command comprises a logical address,
• divide the logical address into a most significant bits portion and a least significant bits portion,
• transmit the most significant bits portion to multiple address translation tables;
• retrieving a set of entries comprising an entry from each of the multiple address translation tables, wherein each of the set of entries comprises:
• (a) most significant bits of a non-volatile physical address,
• (b) most significant bits of a volatile physical address, and
• (c) flags indicating whether a value is valid;
• transmit the flags from the set entries to a select block to select at most one of the most significant bits of the non-volatile physical address and at most one of the most significant bits of the volatile physical address;
• and
• merge the least significant bits portion with at least one of the at most one of the most significant bits of the non-volatile physical address and at most one of the most significant bits of the volatile physical address.