Latching data for output at an edge of a clock signal generated in response to an edge of another clock signal

A method of operating a memory device to latch data for output from the memory device, comprising:

• generating a clock pulse of a first clock signal, the clock pulse of the first clock signal comprising a first edge and a second, opposite, edge;
• generating a clock pulse of a second clock signal, the clock pulse of the second clock signal comprising a first edge generated in response to the first edge of the clock pulse of the first clock signal and a second, opposite, edge generated in response to the second edge of the clock pulse of the first clock signal;
• outputting the data from a data cache of the memory device in response to the first edge of the clock pulse of the first clock signal;
• and
• latching the data to a read buffer of the memory device for output from the memory device in response to the second clock edge of the clock pulse of the second clock signal.

A method of operating a memory device to latch first and second data for output from the memory device, comprising:

• generating a first clock signal comprising a synchronous portion generated in response to a first portion of a second clock signal having a first frequency and an asynchronous portion generated in response to a second portion of the second clock signal having a second frequency less than the first frequency;
• latching the first data for output from the memory device in response to a clock edge in the synchronous portion of the first clock signal and generated in response to a clock edge in the first portion of the second clock signal;
• and
• latching the second data for output from the memory device in response to a clock edge in the asynchronous portion of the first clock signal and generated in response to a signal that is different than the first and second clock signals.