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AssigneeQUALCOMM Incorporated
InventorsMilind Ram KULKARNI, Rami Mohammad A. AL SHEIKH, Raguram DAMODARAN
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A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.
A scheduler, comprising:
A method of scheduling instructions in a scheduler, the method comprising:
The method of 13, repeating the evaluating the instruction in a next cycle when it is determined that the instruction is not ready in a previous cycle.
A scheduler, comprising:
Dependencies are inferred from the claim text.