Frequency Adjustment Method, System-On-Chip, and Terminal

A frequency adjustment method, applied to a System-On-a-Chip (SoC), wherein the SoC comprises a central processing unit (CPU), a service processor, a frequency adjustment module, a spread spectrum clocking generator, and a double data rate synchronous dynamic random access memory (DDR) interface, and wherein the method comprises:

• receiving, by the frequency adjustment module, a first frequency adjustment request sent by the CPU, wherein the first frequency adjustment request is generated by the CPU when an access bandwidth availability which the service processor accesses a DDR memory coupled to the SoC changes, and wherein the first frequency adjustment request comprises an initial frequency at which the DDR interface currently works and a first target frequency;
• determining, by the frequency adjustment module according to the first frequency adjustment request, a first frequency adjustment coefficient of the spread spectrum clocking generator corresponding to the initial frequency, and a second frequency adjustment coefficient of the spread spectrum clocking generator corresponding to the first target frequency;
• obtaining, by the frequency adjustment module, a predetermined adjustment amount by which a frequency adjustment coefficient of the spread spectrum clocking generator is adjusted each time and a predetermined interval between two adjacent adjustments, wherein a frequency adjustment value of the spread spectrum clocking generator corresponding to the predetermined adjustment amount is within a locking-in frequency adjustment range of a phase-locked loop in the spread spectrum clocking generator, wherein a working frequency adjustment value of the DDR interface corresponding to the predetermined adjustment amount is within a locking-in frequency adjustment range of a delay-locked loop (DLL) in the DDR interface and wherein the predetermined interval is within a locking-in time range of the phase-locked loop in the spread spectrum clocking generator and a locking-in time range of the DLL in the DDR interface;
• and
• gradually adjusting, by the frequency adjustment module, the frequency adjustment coefficient of the spread spectrum clocking generator in sequence according to the first frequency adjustment coefficient until the second frequency adjustment coefficient is reached, wherein an amplitude of each adjustment is the predetermined adjustment amount, and wherein a time length between two adjustments is the predetermined interval.

A terminal, comprising:

• a double data rate synchronous dynamic random access memory (DDR) memory;
• and
• a System-On-a-Chip (SoC) comprising:
• a central processing unit (CPU);
• a service processor;
• a DDR interface connected to the DDR memory;
• a spread spectrum clocking generator;
• a DDR controller separately connected to the CPU, the service processor, the spread spectrum clocking generator, and the DDR interface;
• and
• a frequency adjustment module separately connected to the spread spectrum clocking generator and the CPU,
• wherein the service processor is configured to access, using the DDR controller and the DDR interface, the DDR memory coupled to the SoC,
• wherein the spread spectrum clocking generator is configured to receive an input clock rate and output a clock rate to the DDR interface,
• wherein the CPU is configured to generate a first frequency adjustment request and output the first frequency adjustment request to the frequency adjustment module when an access bandwidth availability which the service processor accesses the DDR memory changes,
• wherein the first frequency adjustment request comprises an initial frequency at which the DDR interface currently works and a first target frequency, and
• wherein the frequency adjustment module is configured to:
• determine, according to the first frequency adjustment request, a first frequency adjustment coefficient of the spread spectrum clocking generator corresponding to the initial frequency, and a second frequency adjustment coefficient of the spread spectrum clocking generator corresponding to the first target frequency;
• obtain a predetermined adjustment amount by which a frequency adjustment coefficient of the spread spectrum clocking generator is adjusted each time and a predetermined interval between two adjacent adjustments, wherein a frequency adjustment value of the spread spectrum clocking generator corresponding to the predetermined adjustment amount is within a locking-in frequency adjustment range of a phase-locked loop in the spread spectrum clocking generator, wherein a working frequency adjustment value of the DDR interface corresponding to the predetermined adjustment amount is within a locking-in frequency adjustment range of a delay-locked loop (DLL) in the DDR interface, and wherein the predetermined interval is within a locking-in time range of the phase-locked loop in the spread spectrum clocking generator and a locking-in time range of the DLL in the DDR interface;
• and
• gradually adjust the frequency adjustment coefficient of the spread spectrum clocking generator from the first frequency adjustment coefficient to the second frequency adjustment coefficient in sequence, wherein an amplitude of each adjustment is the predetermined adjustment amount, and wherein a time length between two adjustments is the predetermined interval.