Identification of unknown sources for logic built-in self test in verification

A computer system for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit, the computer system comprising:

• one or more computer processors;
• one or more computer readable storage media;
• program instructions stored on at least one of the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
• responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, program instructions to determine whether a latch of the one or more latches is corrupted by an unknown source;
• program instructions to gather each of the one or more latches determined to be an unknown source after a capture clock phase;
• program instructions to perform a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source;
• and
• program instructions to verify that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

A computer program product for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit, the computer program product comprising:

• one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:
• responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, program instructions to determine whether a latch of the one or more latches is corrupted by an unknown source;
• program instructions to gather each of the one or more latches determined to be an unknown source after a capture clock phase;
• program instructions to perform a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source;
• and
• program instructions to verify that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.