Wafer-level chip package structure and packaging method

A wafer-level chip package structure, comprising:

• a substrate comprising a plurality of sensing chip areas, wherein the substrate has a first surface and a second surface which is opposite to the first surface, and each of the sensing chip areas comprises a sensing area located on the first surface;
• a cover layer located on the first surface of the substrate;
• and
• a plug structure located in each of the sensing chip areas of the substrate, wherein one end of the plug structure is electrically connected with the sensing area, and the other end of the plug structure is exposed by the second surface of the substrate.

A wafer-level chip packaging method, comprising:

• providing a substrate which comprises a plurality of sensing chip areas, wherein the substrate has a first surface and a second surface which is opposite to the first surface, and each of the sensing chip areas comprises a sensing area located on the first surface;
• forming a cover layer on the first surface of the substrate;
• and
• forming a plug structure in each of the sensing chip areas of the substrate, wherein one end of the plug structure is electrically connected with the sensing area, and the other end of the plug structure is exposed by the second surface of the substrate.