Low power wideband non-coherent binary phase shift keying demodulator to align the phase of sideband differential output comparators for reducing jitter, using first order sideband filters with phase 180 degree alignment

In the circuit structure of simple low power wideband non-coherent BPSK demodulator using first order sideband filters with phase 180 degree alignment, the simple low power wideband non-coherent binary phase shift keying demodulation circuit comprises:

• a sideband separation and lower sideband signal delay unit to output the upper sideband negative-phase digital signal and the phase delayed digital signal to be delayed with preset phase from lower sideband positive-phase digital signal, when a modulation signal in the input of this unit is divided to the upper sideband and lower sideband analog signals by 1st order filters whose cutoff frequency is same as carrier frequency;
• a data demodulation unit to demodulate data through the symbol edge signal that has glitches for using detecting clock to use above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal, the symbol edge signal whose glitches are eliminated by the Deglitch filter, and the unit demodulates data using above symbol edge signal and above delayed lower sideband positive-phase digital signal;
• and
• a data clock recovery unit to recover data clock using above delayed lower sideband positive-phase digital signal and above demodulated digital data signal, also
• above sideband separation and lower sideband signal delay unit comprises:
• a 1st order low-pass filter (1st order LPF) whose cutoff frequency is same as carrier frequency isolates lower sideband from above modulated signal;
• the first comparator to convert to positive-phase digital signal from lower sideband analog signal that is separated by above 1st order LPF;
• a delay circuit to delay with preset phase from the lower sideband positive-phase digital signal;
• a 1st order high-pass filter (1st order HPF) whose cutoff frequency is same as carrier frequency isolates upper sideband from above modulated signal;
• and
• the second comparator to convert to negative-phase digital signals from upper sideband analog signal that is separated by above 1st order HPF,
• above data demodulation unit comprises:
• an Exclusive-OR gate that compares above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal;
• a Deglitch filter that is a glitch removing circuit in analog or digital type;
• and
• a D-flip-flop whose inputs are data (D) input that is the delayed lower sideband positive-phase digital signal and clock (C) that is above symbol edge signal,
• above data clock recovery unit comprises:
• an exclusive-NOR gate to compare above delayed lower sideband positive-phase digital signal with above demodulated data signal,
• and to be with emphasis in following characteristics:
• the lower sideband positive-phase digital signal that is separated through above 1st order LPF and the first comparator, is occurred as slow as ¼ period of carrier frequency rather than the upper sideband digital signal that is separated through above 1st order HPF and the second comparator, and the delay circuit to delay more ¼ period of carrier frequency for a pair of signals whose phase difference is same as phase 180°, above symbol edge signal that is generated by above Exclusive-OR gate whose inputs are above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal is stable for demodulating data by non-coherent way in low power;
• where above delayed lower sideband digital signal and above upper sideband digital signal are aligned in phase 180° that is the phase to minimize glitches, a pair of digital signals with each opposite phase to align in symbol edges to be compared in same rising edge and same falling edge such as a pair of digital signals that are in the delayed lower sideband positive-phase and upper sideband negative-phase for reducing glitches that are caused by small jitters;
• and
• to improve yield in the high stability of circuit that has above symbol edge signal for small glitches by reducing jitter because the comparator output duty-cycle is changed by the difference of CMOS FET characteristic in fabrication and the input off-set problem of the comparator.

In the flowchart of a low power wideband non-coherent BPSK demodulation method using first order sideband filters with phase 180 degree alignment, a low power wideband non-coherent binary phase shift keying demodulation method comprises:

• a sideband separation and lower sideband signal delay stage to output the upper sideband digital signals and the phase delayed digital signals to be delayed with preset phase from lower sideband digital signals, when a modulation signal in the input of this stage is divided to the upper sideband and lower sideband analog signals by 1st order filters whose cutoff frequency is same as carrier frequency, and the stage generates two pair of positive-phase and negative-phase signals that are upper sideband digital signals and lower sideband digital signals by differential output comparators;
• a data demodulation stage to demodulate data through the first symbol edge signal that has glitches for using detecting clock to use above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal, the second symbol edge signal that has glitches for using detecting clock to use above delayed lower sideband negative-phase digital signal and above upper sideband positive-phase digital signal, the third symbol edge signal whose glitches are reduced by overlapping the first symbol edge signal and the second symbol edge signal, the symbol edge signal whose glitches are eliminated by the Deglitch filter, and the stage demodulates data using above symbol edge signal and above delayed lower sideband positive-phase digital signal;
• and
• a data clock recovery stage to recover data clock using above delayed lower sideband positive-phase digital signal and above demodulated digital data signal, also
• above sideband separation and lower sideband signal delay stage comprises:
• a 1st order low-pass filter (1st order LPF) whose cutoff frequency is same as carrier frequency isolates lower sideband from above modulated signal;
• the first differential output comparator to convert to positive-phase and negative-phase digital signals from lower sideband analog signal that is separated by above 1st order LPF;
• the first delay circuit to delay with preset phase from the lower sideband positive-phase digital signal;
• the second delay circuit to delay with preset phase from the lower sideband positive-phase digital signal;
• a 1st order high-pass filter (1st order HPF) whose cutoff frequency is same as carrier frequency isolates upper sideband from above modulated signal;
• and
• the second differential output comparator to convert to positive-phase and negative-phase digital signals from upper sideband analog signal that is separated by above 1st order HPF,
• above data demodulation stage comprises:
• the first Exclusive-OR gate that compares above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal;
• the second Exclusive-OR gate that compares above delayed lower sideband negative-phase digital signal and above upper sideband positive-phase digital signal;
• an AND gate that generates above third symbol edge signal that is the overlap of above first symbol edge signal and above second symbol edge signal;
• a Deglitch filter that is a glitch removing circuit in analog or digital type;
• and
• a D-flip-flop whose inputs are data (D) input that is the delayed lower sideband positive-phase digital signal and clock (C) that is above symbol edge signal,
• above data clock recovery stage comprises:
• an exclusive-NOR gate to compare above delayed lower sideband positive-phase digital signal with above demodulated data signal,
• and to be with emphasis in following characteristics:
• the lower sideband digital signals that are separated through above 1st order LPF and the first differential output comparator, are occurred as slow as ¼ period of carrier frequency rather than the upper sideband digital signals that are separated through above 1st order HPF and the second differential output comparator, and the delay circuits to delay more ¼ period of carrier frequency for two pair of signals whose phase difference are same as phase 180°, above first symbol edge signal that is generated by above first Exclusive-OR gate whose inputs are above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal and above second symbol edge signal that is generated by above second Exclusive-OR gate whose inputs are above delayed lower sideband negative-phase digital signal and above upper sideband positive-phase digital signal are stable for demodulating data by non-coherent way in low power;
• where above delayed lower sideband digital signals and above upper sideband digital signals are aligned in phase 180° that is the phase to minimize glitches, two pair of digital signals with each opposite phase to align in symbol edges to be compared in same rising edge and same falling edge such as a pair of digital signals that are in the delayed lower sideband positive-phase and upper sideband negative-phase, also another pair of digital signals that are in the delayed lower sideband negative-phase and upper sideband positive-phase for reducing glitches that are caused by minimum jitters;
• and
• to improve yield in the high stability of circuit that has above third symbol edge signal which is generated from the overlap of above first symbol edge signal and above second symbol edge signal for minimizing glitches by reducing jitter because the output duty-cycle of sideband differential output comparators is changed by the difference of CMOS FET characteristic in semiconductor fabrication and the input off-set problem of the comparator.

In the flowchart of simple low power wideband non-coherent BPSK demodulation method using first order sideband filters with phase 180 degree alignment, simple low power wideband non-coherent binary phase shift keying demodulation method comprises:

• a sideband separation and lower sideband signal delay stage to output the upper sideband negative-phase digital signal and the phase delayed digital signal to be delayed with preset phase from lower sideband positive-phase digital signal, when a modulation signal in the input of this stage is divided to the upper sideband and lower sideband analog signals by 1st order filters whose cutoff frequency is same as carrier frequency;
• a data demodulation stage to demodulate data through the symbol edge signal that has glitches for using detecting clock to use above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal, the symbol edge signal whose glitches are eliminated by the Deglitch filter, and the stage demodulates data using above symbol edge signal and above delayed lower sideband positive-phase digital signal;
• and
• a data clock recovery stage to recover data clock using above delayed lower sideband positive-phase digital signal and above demodulated digital data signal, also
• above sideband separation and lower sideband signal delay stage comprises:
• a 1st order low-pass filter (1st order LPF) whose cutoff frequency is same as carrier frequency isolates lower sideband from above modulated signal;
• the first comparator to convert to positive-phase digital signal from lower sideband analog signal that is separated by above 1st order LPF;
• a delay circuit to delay with preset phase from the lower sideband positive-phase digital signal;
• a 1st order high-pass filter (1st order HPF) whose cutoff frequency is same as carrier frequency isolates upper sideband from above modulated signal;
• and
• the second comparator to convert to negative-phase digital signals from upper sideband analog signal that is separated by above 1st order HPF,
• above data demodulation stage comprises:
• an Exclusive-OR gate that compares above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal;
• a Deglitch filter that is a glitch removing circuit in analog or digital type;
• and
• a D-flip-flop whose inputs are data (D) input that is the delayed lower sideband positive-phase digital signal and clock (C) that is above symbol edge signal,
• above data clock recovery stage comprises:
• an exclusive-NOR gate to compare above delayed lower sideband positive-phase digital signal with above demodulated data signal,
• and to be with emphasis in following characteristics:
• the lower sideband positive-phase digital signal that is separated through above 1st order LPF and the first comparator, is occurred as slow as ¼ period of carrier frequency rather than the upper sideband digital signal that is separated through above 1st order HPF and the second comparator, and the delay circuit to delay more ¼ period of carrier frequency for a pair of signals whose phase difference is same as phase 180°, above symbol edge signal that is generated by above Exclusive-OR gate whose inputs are above delayed lower sideband positive-phase digital signal and above upper sideband negative-phase digital signal is stable for demodulating data by non-coherent way in low power;
• where above delayed lower sideband digital signal and above upper sideband digital signal are aligned in phase 180° that is the phase to minimize glitches, a pair of digital signals with each opposite phase to align in symbol edges to be compared in same rising edge and same falling edge such as a pair of digital signals that are in the delayed lower sideband positive-phase and upper sideband negative-phase for reducing glitches that are caused by small jitters;
• and
• to improve yield in the high stability of circuit that has above symbol edge signal for small glitches by reducing jitter because the comparator output duty-cycle is changed by the difference of CMOS FET characteristic in fabrication and the input off-set problem of the comparator.