Bi-directional snapback esd protection circuit
AssigneeMonolithic Power Systems, Inc.
InventorEric Braun
Life of this patent
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Abstract
An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.
Claims11
An ESD protection circuit coupled between a first node and a second node, wherein at the first node exits a first voltage, and at the second node exits a second voltage, the ESD protection circuit comprising:
- a discharging transistor having a drain, a gate, a source and a body, wherein the drain is coupled to the first node, the source is coupled to the second node, the gate is coupled to the body;
- and
- a body snatching circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first node, the second input terminal is coupled to the second node, and the output terminal is coupled to the body, and wherein the body snatching circuit is configured to output either the first voltage or the second voltage at the output terminal, based on which of the first voltage and the second voltage has a lower value.
A semiconductor structure for protecting an integrated circuit coupled between a first node and a second node from ESD damage, comprising:
- a semiconductor layer having a first conductivity type and a top surface;
- a first well, a second well, a third well and a fourth well all having a second conductivity type opposite to the first conductivity type, wherein the first, second, third and fourth wells are located in the semiconductor layer adjoining the top surface and are isolated from each other by the semiconductor layer, and wherein the first, second, third and fourth wells are arranged in sequence with respect to the lateral direction of the semiconductor layer;
- a first gate, a second gate and a third gate, wherein the first, second and third gates are located insulatively above the top surface of the semiconductor layer, and wherein the first gate overlaps laterally with a portion of both the first and second wells, the second gate overlaps laterally with a portion of both the second and third wells, and the third gate overlaps laterally with a portion of both the third and fourth wells;
- and
- wherein the second well and the third gate are coupled to the first node, the second gate and the first and fourth wells are coupled to the second node, and the first gate and the third well are electrically coupled to the semiconductor layer.
Dependencies are inferred from the claim text.