US 2017/0256629 A1Published application

Method for manufacturing semiconductor element and method for forming mask pattern of the same

AssigneeKabushiki Kaisha Toshiba

InventorMasafumi HAMAGUCHI

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Abstract

A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.

Claims16

Dependent claims

A method for manufacturing a semiconductor element, the method comprising:

forming a first region of a first conductivity type in a semiconductor region by selectively ion-implanting impurities of the first conductivity type using a first mask provided on the semiconductor region, the first mask having a first opening, the first region being exposed at a bottom surface of the first opening;
forming an interconnect including a gate portion extending in a first direction over the first region;
and
forming a source and a drain by ion-implanting impurities of a second conductivity type into a second region, the second region being positioned on two sides of the gate portion in the first region,
a gate threshold voltage of the semiconductor element having:
a first correlation dependent on a first distance to an inner wall of the first opening from an outer edge of the second region proximal to the inner wall of the first opening,
a second correlation dependent on a second distance from the outer edge of the second region to the gate portion in a second direction intersecting the first direction,
a third correlation dependent on a third distance in one of the first direction and the second direction to the outer edge of the second region from a portion of the interconnect positioned outside the second region, and
a fourth correlation dependent on a fourth distance when impurities of the first conductivity type are selectively ion-implanted under the gate portion using a second mask provided on the semiconductor region, the fourth distance being the distance to an inner wall of a second opening of the second mask from the outer edge of the second region proximal to the inner wall of the second opening, and
at least one of the first distance, the second distance, the third distance, and the fourth distance being determined based on the first correlation, the second correlation, the third correlation and the fourth correlation to obtain a prescribed gate threshold voltage of the semiconductor element.

7 more elements

A method for forming a mask pattern of a semiconductor element, the method comprising:

forming a mask pattern group based on a prescribed rule of providing the semiconductor element with a first gate threshold voltage, the mask pattern group including:
a well pattern defining a first region on a semiconductor region;
an interconnect pattern defining an interconnect including a gate portion extending in a first direction on the first region;
and
a source/drain pattern defining a second region positioned in the first region, the gate portion crossing the second region in the first direction.
modifying at least one of a first distance, a second distance, a third distance and a fourth distance based on a first correlation, a second correlation, a third correlation and a fourth correlation of a gate threshold voltage of the semiconductor element to obtain a second gate threshold voltage, wherein
the gate threshold voltage in the first correlation depends on the first distance to an outer edge of the first region from an outer edge of the second region proximal to the outer edge of the first region;
the gate threshold voltage in the second correlation depends on the second distance from the outer edge of the second region to the gate portion in a second direction intersecting the first direction;
the gate threshold voltage in the third correlation depends on the third distance to the second region from a portion of the interconnect positioned outside the second region in one of the first direction or the second direction;
and
the gate threshold voltage in the fourth correlation depends on the fourth distance when the mask pattern group further includes an ion implantation pattern defining an opening exposing the gate portion, the fourth distance being the distance to a wall surface of the opening from the outer edge of the second region proximal to the wall surface of the opening.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/263,800Filed 13 Sep 2016
Priority: 3 Mar 2016
Published: 7 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10P 30/204
Characterised by the semiconductor materials: into Group IV semiconductors

Family

Application62/303,247Us provisional application · filed 3 Mar 2016
US 10,366,913 B2Related patent
US 2017/0256629 A1This patent

From the US filing history. Foreign family members aren’t listed.

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