Common metal contact regions having different schottky barrier heights and methods of manufacturing same

A method comprising:

• providing a substrate having an n-FET region and a p-FET region separated by a shallow trench isolation (STI) region, each of the n-FET and p-FET regions including a gate between source/drain regions;
• forming an interlayer dielectric (ILD) over the substrate, with trenches formed through the ILD down to the source/drain regions;
• applying a mask over the n-FET region;
• implanting a dopant into the p-FET region source/drain regions through the trenches in the ILD;
• selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked;
• removing the mask;
• depositing a titanium-based metal in the trenches over the n-FET and p-FET region source/drain regions;
• and
• microwave annealing.