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US 2017/0256590 A1Published application
Block architecture for vertical memory array
AssigneeSony Corporation
InventorJun Sumino
Life of this patent
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Abstract
Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.
Claims11
A memory device, comprising:
- at least one memory array configured to include a plurality of memory cells;
- a plurality of word lines (WL);
- and
- a plurality bit lines (BL),
- wherein each of the plurality of memory cells is configured to be located between the plurality of word lines and the plurality of bit lines and the plurality of word lines cross the plurality of bit lines.
2 more elements
Dependencies are inferred from the claim text.