Thin film transistor array panel

A thin film transistor array panel comprising:

• a substrate;
• gate lines on the substrate, each of the gate lines comprising a gate electrode;
• a semiconductor layer on the substrate;
• a gate insulating layer between the gate electrode and the semiconductor layer;
• an etching stopper on the semiconductor layer;
• a data wiring layer on the substrate, the data wiring layer comprising a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode;
• and
• a passivation layer covering the source electrode, the drain electrode, and the etching stopper,
• wherein the etching stopper comprises an etching prevention portion between the source electrode and the drain electrode,
• a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and
• a width of a channel portion of the semiconductor layer is greater than the shortest distance A, and
• the etching stopper is an island on the semiconductor layer.