Manufacturing method of non-volatile semiconductor memory device and non-volatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHiroaki NAITO
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Abstract
According to one embodiment, a conductive layer is patterned based on a first mask pattern to form word lines extending in a cell array region in a row direction, a slit is formed in the conductive layer in a peripheral region to form first air gaps between the word lines, a first insulation film is formed on the conductive layer to cover the slit, the conductive layer is patterned based on a second mask pattern to form select gate lines extending in the cell array region in the row direction, and the conductive layer in the peripheral region is divided in a column direction.
Claims20
A manufacturing method of a non-volatile semiconductor memory device in which memory cells are arranged in a cell array region in a row direction and a column direction, comprising:
- forming a conductive layer in the cell array region and a peripheral region;
- patterning the conductive layer based on a first mask pattern formed by first lithography to form word lines extending in the cell array region in the row direction and form a slit in the conductive layer in the peripheral region;
- forming a first insulation film on the conductive layer to cover the word lines such that a first air gap is generated between the word lines and cover the slit;
- and
- patterning the conductive layer based on a second mask pattern formed by second lithography to form select gate lines extending in the cell array region in the row direction and separate the conductive layer in the peripheral region in the column direction to form gate electrodes divided by the slit in the row direction in the peripheral region.
A non-volatile semiconductor memory device, comprising:
- a memory cell array in which memory cells are arranged in a row direction and a column direction and word lines are arranged in the row direction,
- first air gaps provided between the word lines;
- a peripheral circuit provided around the memory cell array;
- second air gaps provided between gate electrodes of the peripheral circuit;
- and
- a first insulation film that is provided on the word lines and the gate electrodes, and is in contact with the upper ends of the first air gaps and the upper ends of the second air gaps.
Dependencies are inferred from the claim text.