Single mask level including a resistor and a through-gate implant

A method of forming an integrated circuit (IC), comprising:

• providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of said semiconductor surface layer including a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area;
• depositing a polysilicon layer over said CMOS transistor area to provide a polysilicon gate area for MOS transistors in said CMOS transistor area, over said BSD class device area, and over said field dielectric for providing a polysilicon resistor in said resistor area;
• forming a first mask pattern on said polysilicon layer;
• using said first mask pattern, first implanting (I1) said polysilicon resistor with a first dopant at a first implant energy providing a first projected range (RP1) for said first dopant that is less than (<) a thickness of said polysilicon layer;
• using said first mask pattern, second implanting (I2) with a second dopant at a second implant energy providing a second RP (RP2), wherein said RP2>said RP1, said I2 providing at least one of a CMOS implant into said semiconductor surface layer in said CMOS transistor area and a BSD implant into said semiconductor surface layer in said BSD class device area.