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AssigneesCommissariat à I'Énergie Atomique et aux Énergies Alternatives, STMcroelectronics S.A., Centre National De La Recherche Scientifique
InventorsYohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
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A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
1-34. (canceled)
A manufacture comprising an integrated circuit comprising a protection device for protection of said integrated circuit against electrostatic discharge, said protection comprising, first and second electrodes, a buried insulant layer, a first bipolar transistor, a second bipolar transistor, and a first semiconductor ground plane, wherein said buried insulant layer has a thickness that is no greater than fifty nanometers, wherein said first and second bipolar transistors are arranged on said buried insulant layer, wherein one of said first and second bipolar transistors is an NPN transistor, wherein another of said first and second bipolar transistors is a PNP transistor, wherein a base of said first bipolar transistor merges with a collector of said second bipolar transistor, wherein a base of said second bipolar transistor merges with a collector of said first bipolar transistor, wherein said first and second bipolar transistors are configured for selectively conducting a discharge current between said first and second electrodes, wherein said first semiconductor ground plane is arranged under said buried insulant layer, wherein said first semiconductor ground plane is capable of being electrically biased, wherein said first semiconductor ground plane extends underneath said base of said first bipolar transistor, wherein said first semiconductor ground plane has a first type of doping, wherein said base of said first bipolar transistor has said first type of doping, and wherein said first semiconductor ground plane has a dopant density that is at least ten times greater than a dopant density of said base of said first bipolar transistor.
A method comprising fabricating an integrated circuit, wherein fabricating said integrated circuit comprises forming a first semiconductor ground plane by implanting a first type of dopant into a semiconductor substrate that is arranged under a buried insulant layer, said buried insulant layer having a thickness less than or equal to 50 nm, forming first and second bipolar transistors on said buried insulant layer, wherein one of said first and second transistors is an NPN transistor and an other of said first and second transistors is a PNP transistor, wherein a base of said first transistor has said first type of dopant, wherein said base of said first transistor and a base of said second transistor merge with respective collectors of said second and first bipolar transistors, wherein said base of said first bipolar transistor is formed underneath said first semiconductor ground plane, wherein doping of said base of said first transistor is performed during implantation of said first type of dopant for formation of said first semiconductor ground plane, wherein a dopant density upon completion of said implantation in said first semiconductor ground plane is at least ten times greater than a dopant density of said base of said first bipolar transistor.
Dependencies are inferred from the claim text.