Semiconductor memory device including output buffer
AssigneeMicron Technology, Inc.
InventorsWataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
Life of this patent
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Abstract
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.
Claims21
A memory module comprising:
- a module substrate;
- a first plurality of memory chips mounted on the module substrate, the first plurality of memory chips including:
- a first memory chip;
- a second memory chip;
- and
- a group of third memory chips, wherein the second memory chip is arranged between the first memory chip and the group of third memory chips;
- a first line pattern provided on the module substrate, the first line pattern extending along the first plurality of memory chips, the first line pattern including:
- a first branching point coupled to the first memory chip;
- a second branching point coupled to the second memory chip;
- a group of third branching points coupled respectively to the group of third memory chips, wherein the second branching point is arranged between the first branching point and the group of the third branching points;
- and
- a fourth branching point arranged between the first branching point and the second branching point;
- and
- a first termination resistor arranged between the first memory chip and the second memory chip and mounted on the module substrate, the first termination resistor including a first end coupled to a terminal power source and a second end,
- wherein the fourth branching point is coupled to the second end of the first termination resistor.
The memory module of claim 16, wherein the first memory chip, the first termination resistor, the second memory chip and the register chip are aligned along a first line, and the third memory chip and the fourth memory chip are aligned along a second line substantially parallel to the first line.
A memory module comprising:
- a module substrate;
- a line pattern provided on the module substrate, the line pattern including:
- a first branching point;
- a second branching point;
- and
- a third branching point;
- a first partial line pattern extending from the first branching point to the second branching point, wherein the first partial line pattern includes:
- a fourth branching point;
- and
- a fifth branching point between the fourth branching point and the first branching point, wherein the fourth branching point is being between the second branching point and the fifth branching point;
- and
- a second partial hue pattern extending from the first branching point to the third branching point, the second partial line pattern including:
- a sixth branching point;
- and
- a seventh branching point between the sixth branching point and the first branching point, wherein the sixth branching point is being between the third branching point and the seventh branching point;
- a first memory chip mounted on the module substrate and coupled to the second branching point;
- a second memory chip mourned on the module substrate and coupled to the fifth branching point;
- a first termination resistor mounted on the module substrate between the first memory chip and the second memory chip and coupled to the fourth branching point;
- a second termination resistor mounted on the module substrate and coupled to the third branching point;
- a third memory chip mounted on the module substrate and coupled to the sixth branching point;
- and
- a fourth memory chip mounted on the module substrate and coupled to the seventh branching point.
Dependencies are inferred from the claim text.