Stub minimization for wirebond assemblies without windows

A microelectronic package, comprising:

• a substrate having first and second opposed surfaces and pluralities of first, second, third, and fourth substrate contacts exposed at the first surface, the first and second surfaces each extending in a first direction and in a second direction transverse thereto;
• first, second, third, and fourth microelectronic elements each having memory storage array function, each microelectronic element having a rear face facing the first surface, a front face opposite the first surface, parallel first edges each extending in the first direction and between the front and rear faces, and parallel second edges each extending in the second direction and between the front and rear faces, each microelectronic element having one or more columns of element contacts exposed at the respective front face, each column extending in the first direction along the respective front face;
• conductive structure extending above the front faces electrically connecting the element contacts of the first, second, third, and fourth microelectronic elements with the first, second, third, and fourth substrate contacts, respectively;
• and
• a plurality of terminals exposed at the second surface and electrically connected with the substrate contacts,
• wherein the microelectronic elements are spaced apart from one another on the first surface, the front faces of the microelectronic elements extend parallel to the first surface, one of the first edges of the first microelectronic element is aligned with and adjacent to one of the first edges of the second microelectronic element, one of the second edges of the first microelectronic element is aligned with and adjacent to one of the second edges of the fourth microelectronic element, one of the second edges of the third microelectronic element is aligned with and adjacent to one of the second edges of the second microelectronic element, and one of the first edges of the third microelectronic element is aligned with and adjacent to one of the first edges of the fourth microelectronic element.