Soc with integrated voltage regulator using preformed mim capacitor wafer

An integrated circuit, comprising:

• a semiconductor die;
• a plurality of wiring layers, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers, and wherein the plurality of wiring layers further include conductors to couple the semiconductor die from a first surface of the plurality of wiring layers that abuts the semiconductor die to a second surface of the plurality of wiring layers that is opposite to the first surface;
• a redistribution layer coupled to the plurality of wiring layers;
• a circuit including at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die, the circuit arranged substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers;
• and
• a plurality of electrical connectors to couple the integrated circuit to a circuit board, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit.