Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

A semiconductor device, comprising:

• a first conductive element disposed in a first dielectric layer;
• an etching stop layer disposed on the first dielectric layer but not on the first conductive element;
• a first metal capping layer segment disposed on the first conductive element but not on the first dielectric layer, wherein the etching stop layer has a greater thickness than the first metal capping layer segment;
• a second conductive element, wherein a first segment of the second conductive element is disposed on the first metal capping layer segment, and wherein a second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer;
• and
• a third conductive element disposed over the second conductive element

A method, comprising:

• forming a plurality of metal capping layer segments over a plurality of first conductive elements, respectively, the plurality of first conductive elements being disposed in a first dielectric layer;
• forming an etching stop layer over the first dielectric layer;
• forming a hard mask layer over the etching stop layer and over the plurality of metal capping layer segments;
• polishing the hard mask layer until the hard mask layer and the etching stop layer have co-planar upper surfaces;
• forming a dielectric layer over the co-planar upper surfaces of the hard mask layer and the etching stop layer;
• and
• replacing a portion of the hard mask layer formed over at least one of the metal capping layer segments with a second conductive element.