Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof

A method of forming a wafer level chip scale package (WLCSP), the method comprising:

• providing a device chip and a carrier chip, the device chip having a first surface and a second surface, a pad structure having a plurality of metal pads being embedded in the device chip, the metal pads being in parallel and electrically connected to each other, the carrier chip having a third surface and a fourth surface;
• attaching the second surface of the device chip to the third surface of the carrier chip;
• forming at least an offset pad on the first surface of the device chip, wherein the offset pad is electrically connected to the metal pads;
• disposing a device on the first surface of the device chip;
• forming a conductive spacing bump on the offset pad;
• forming an adhesive spacing layer on the first surface of the device chip to encapsulate the conductive spacing bump;
• adhering a protection shield to the adhesive spacing layer to protect the device;
• forming a through hole via, wherein the through hole via comprises a through hole and a hole metal layer, the through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad;
• forming a protection layer on the fourth surface to cover the through hole;
• and
• forming a plurality of terminals on the fourth surface, wherein the terminals penetrate through the protection layer.