US 2017/0256468 A1 · TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE METALIZATION

Abstract

Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

Claims20

Dependent claims

A method comprising:

fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure;
performing a first functional test on a first circuit positioned within the intermediate metal level;
fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure;
and
performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

2 more elements

A method comprising:

fabricating a partial IC structure having a first plurality of metal levels, the first plurality of metal levels including a first metal level and at least one intermediate metal level;
electrically testing a first circuit within the partial IC structure, wherein the electrically testing of the first circuit includes applying a first test current and a second test current to the first circuit, the second test current having a reversed polarity relative to the first test current;
fabricating a second plurality of metal levels on the partial IC structure to yield the completed IC structure, wherein the second plurality of metal levels includes a capping metal level, and wherein the fabricating of the second plurality of metal levels on the partial IC structure yields an electrical short in the first circuit;
and
electrically testing a second circuit within the completed IC structure after fabricating the second plurality of metal levels, wherein the electrically testing of the second circuit includes applying a test voltage to the second circuit, the second circuit being a circuit of the completed IC structure other than the first circuit.

2 more elements

Dependencies are inferred from the claim text.

Test method and structure for integrated circuits before complete metalization

Life of this patent

Test method and structure for integrated circuits before complete metalization

Life of this patent

Abstract

Claims20