Complementary nanowire semiconductor device and fabrication method thereof

Abstract

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

Dependencies are inferred from the claim text.