US 2017/0256458 A1 · SEMICONDUCTOR DEVICES, FINFET DEVICES, AND METHODS OF FORMING THE SAME

Abstract

Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first region, and a first end sidewall of the first gate is faced to a second end sidewall of the second gate. Third and fourth gates are on the substrate in the second region, and a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate. A dielectric layer is between the first and second gates and between the third and fourth gates. The first and second regions have different pattern densities, and an included angle between the substrate and a sidewall of the dielectric layer between the first and second gates is different from an included angle between the substrate and a sidewall of the dielectric layer between the third and fourth gates.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate having a first region and a second region;
a first gate and a second gate on the substrate in the first region, wherein a first end sidewall of the first gate is faced to a second end sidewall of the second gate;
a third gate and a fourth gate on the substrate in the second region, wherein a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate;
and
a dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate and between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate,
wherein a pattern density of the first region is different from a pattern density of the second region, and an included angle between the substrate and a sidewall of the dielectric layer between the first gate and the second gate is different from an included angle between the substrate and a sidewall of the dielectric layer between the third gate and the fourth gate.

3 more elements

A FinFET device, comprising:

a substrate having at least one first fin and at least one second fin in a first region and having at least one third fin and at least one fourth fin in a second region;
a first gate across the at least one first fin and a second gate across the at least one second fin, wherein a first end sidewall of the first gate is faced to a second end sidewall of the second gate;
a third gate across the at least one third fin and a fourth gate across the at least one fourth fin, wherein a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate;
and
a dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate and between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate,
wherein a distance from the first end sidewall of the first gate to a sidewall of the at least one first fin is at least two times a distance from the third end sidewall of the third gate to a sidewall of the at least one third fin, and the dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate has a cross-sectional profile different from that of the dielectric layer between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor devices, finfet devices, and methods of forming the same

Life of this patent

Semiconductor devices, finfet devices, and methods of forming the same

Life of this patent

Abstract

Claims20