Semiconductor device including standard cell and electronic design automation method thereof

An electronic design automation method of automatically designing a semiconductor device, the method comprising:

• generating standard cells each having a unit height, using a layout tool;
• generating site-rows each having the unit height and generating metal routing tracks for each of the site-rows and which begin at an offset point spaced a specific distance from an origin point of the site-row, using an electronic design automation (EDA) tool;
• and
• laying out the standard cells on the site-rows and laying out metal lines of interconnection layers of the semiconductor device and points of connection between the metal lines and the standard cells, using a P&R (place and route) tool,
• wherein the metal lines of one of the interconnection layers and points of connection thereof with the standard cells are laid out along the metal routing tracks, and
• the unit height is a non-integer multiple of a spacing of the metal lines of one of interconnection layers.

A method of manufacturing a semiconductor device, the method comprising:

• an electronic automated design process of generating a layout of the semiconductor device including:
• producing a set of standard cells each comprising a two-dimensional representation of an electronic component of the semiconductor device, and wherein one of the two dimensions of each of the standard cells is standardized so that said one of the dimensions has the same value among the standard cells,
• producing site-rows disposed side-by-side and collectively corresponding to a footprint of the semiconductor device, each of the site-rows comprising a two-dimensional frame, one of the dimensions of the frame being a width of the frame and the other of the dimensions being the same as the standardized dimension,
• generating an overlay of metal routing tracks for each of the site-rows, wherein, for each of the site rows, the metal routing tracks begin at a point offset from an origin located along a width-wise side of the frame of the site-row,
• laying out the standard cells in the site-rows each as confined within the frame of a respective one of the site-rows and with the standardized dimensions of the standard cells all oriented in a first direction parallel to the standardized dimensions of the frames of the site-rows;
• and
• fabricating a semiconductor device conforming to the layout by forming the electronic components represented by the standard cells on a substrate, forming interconnection layers of metal lines one above another on the substrate, and connecting the metal lines to the electronic components, and
• wherein the metal lines of one of the interconnection layers extend parallel and linearly along tracks corresponding to the metal routing tracks,
• the metal lines of said one of the interconnection layers have a substantially uniform line-to-line spacing, and
• the standardized dimension is not equal to the product of any integer and the line-to-line spacing of said one of the interconnection layers.