Universal process kit
AssigneeApplied Materials, Inc.
InventorsOlivier JOUBERT, Jason A. KENNEY, Sunil SRINIVASAN, James ROGERS, Rajinder DHINDSA, Vedapuram S. ACHUTHARAMAN, Olivier LUERE
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AssigneeApplied Materials, Inc.
InventorsOlivier JOUBERT, Jason A. KENNEY, Sunil SRINIVASAN, James ROGERS, Rajinder DHINDSA, Vedapuram S. ACHUTHARAMAN, Olivier LUERE
Estimating the term…
The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.
A process kit suitable for use in a semiconductor process chamber, comprising:
A plasma chamber for performing a semiconductor process on a substrate, comprising:
A process kit suitable for use in a process chamber, comprising:
Dependencies are inferred from the claim text.