Overmolded chip scale package
AssigneeNexperia B.V.
InventorsFrank Burmeister, Chi Ho Leung, Zhigang Li, Yujun Zhao, Karen Kirchheimer, Hans-Martin Ritter
Life of this patent
Estimating the term…
Loading patent…
AssigneeNexperia B.V.
InventorsFrank Burmeister, Chi Ho Leung, Zhigang Li, Yujun Zhao, Karen Kirchheimer, Hans-Martin Ritter
Estimating the term…
A method of packing a semiconductor device is disclosed. The method includes placing a wafer on a carrier such that a backside of the wafer is facing up and a front side is facing down and non-permanently affixed to the surface of the carrier, performing lithography to mark area to be etched on the backside of the wafer, etching the marked areas from the backside of the wafer thus forming trenches that mark boundaries of individual devices on the wafer, applying a protective coating on the backside of the wafer thus filling the trenches and entire backside of the wafer with a protective compound and cutting the individual devices from the wafer.
A method of packing a semiconductor device, the method comprising:
A semiconductor device packaged using an operation on a backside of a wafer, the operation comprising:
Dependencies are inferred from the claim text.