Trim method for patterning during various stages of an integration scheme
AssigneeTokyo Electron Limited
InventorsAngelique Raley, Akiteru Ko
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AssigneeTokyo Electron Limited
InventorsAngelique Raley, Akiteru Ko
Estimating the term…
Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APL), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.
A method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising:
A method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising:
Dependencies are inferred from the claim text.