Back to results
US 2017/0256325 A1Published application
Low cost inbuilt deterministic tester for soc testing
AssigneeIntel Corporation
InventorsLakshminarayana PAPPU, Timothy J. CALLAHAN, Tomer LEVY
Life of this patent
Estimating the term…
Abstract
A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.
Claims21
A multi-core system on a chip comprising:
- a first processing core;
- a second processing;
- and
- an auto-response unit at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.
1 more element
A method of testing an integrated circuit, comprising:
- transitioning an auto-response module into a test mode;
- sending a read transaction from a transaction agent;
- intercepting the read transaction in the auto-response module;
- and
- sending a deterministic response to the transaction agent based on the read transaction.
2 more elements
An on-chip test component, comprising:
- a mode selector to select between a test mode and a functional mode;
- an encoder to encode a logical address into a deterministic return value;
- and
- masking logic to mask one or more bits of the return value responsive to a signal from a transaction agent.
1 more element
A chip having on-chip test functionality comprising:
- a transaction agent;
- means for accumulating non-deterministic signatures of write transactions from the transaction agent;
- and
- means for automatically responding with a deterministic return value when a read transaction is received from the transaction agent.
1 more element
Dependencies are inferred from the claim text.