US 2017/0256312 A1 · MEMORY DEVICE

Abstract

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Claims21

Dependent claims

A memory device, comprising:

a substrate;
a first interconnect extending in a first direction, the first direction being parallel to a major surface of the substrate;
a second interconnect extending in a second direction, the second direction crossing the first direction and being parallel to the major surface of the substrate;
a first variable resistance member connected between the first interconnect and the second interconnect;
a third interconnect extending in the first direction;
a second variable resistance member connected between the second interconnect and the third interconnect;
a fourth interconnect extending in the first direction being insulated from the third interconnect;
a fifth interconnect extending in the second direction;
and
a third variable resistance member connected between the fourth interconnect and the fifth interconnect,
the first interconnect, the second interconnect, the third interconnect, the fourth interconnect and the fifth interconnect being arranged along a third-direction in this order, and the third direction crossing the first direction and the second direction.

8 more elements

A memory device, comprising:

a substrate;
and
a plurality of memory cell structure bodies arranged along a first direction, the substrate and the plurality of memory cell structure bodies being arranged along the first direction, the first direction crossing a major surface of the substrate,
each of the memory cell structure bodies including:
a first interconnect layer;
a second interconnect layer;
a third interconnect layer disposed between the first interconnect layer and the second interconnect layer;
a first variable resistance member layer disposed between the first interconnect layer and the third interconnect layer;
and
a second variable resistance member layer disposed between the second interconnect layer and the third interconnect layer,
the first interconnect layer, the second interconnect layer and the third interconnect layer being arranged along the first direction in this order,
the first interconnect layer including a plurality of first interconnects extending in a second direction, the second direction being parallel to the major surface of the substrate,
the second interconnect layer including a plurality of second interconnects extending in the second direction,
the third interconnect layer having a plurality of third interconnects extending in a third direction, the third direction being parallel to the major surface of the substrate and crossing the second direction,
the first variable resistance member layer including first variable resistance members connected between the first interconnects and the third interconnects,
the second variable resistance member layer including second variable resistance members connected between the second interconnects and the third interconnects.

13 more elements

Dependencies are inferred from the claim text.

Memory device

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Memory device

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Abstract

Claims21