Resistance random access memory device and method for operating same

A resistance random access memory device, comprising:

• a first interconnect layer including a plurality of first interconnects, the plurality of first interconnects extending in a first direction and being arranged along a second direction, the second direction crossing the first direction;
• a second interconnect layer including a plurality of second interconnects and being arranged in a third direction with the first interconnect layer, the third direction being orthogonal to both the first direction and the second direction, the plurality of second interconnects extending in the second direction and being arranged along the first direction;
• variable resistance members connected between the first interconnects and the second interconnects, the variable resistance member including
• a metal layer, and
• a variable resistance layer disposed between the first interconnect and the metal layer, a resistivity of the variable resistance layer being higher than a resistivity of the metal layer;
• and
• a control circuit applying a first voltage to the variable resistance member for a first time when switching the variable resistance member from a low resistance state to a high resistance state, the first voltage making a potential of the first interconnect higher than a potential of the second interconnect, and the control circuit applying a second voltage to the variable resistance member for a second time after applying the first voltage when the resistance state of the variable resistance member is in the low resistance state, the second voltage having the same polarity as the first voltage and being lower than the first voltage, the second time being longer than the first time.

A method for operating a resistance random access memory device, the resistance random access memory device including a first interconnect layer, a second interconnect layer, and variable resistance members, the first interconnect layer including a plurality of first interconnects, the plurality of first interconnects extending in a first direction and being arranged along a second direction, the second direction crossing the first direction, the second interconnect layer including a plurality of second interconnects, the plurality of second interconnects extending in the second direction and being arranged along the first direction, the second interconnect layer being arranged in a third direction with the first interconnect layer, the third direction being orthogonal to both the first direction and the second direction, the variable resistance members being connected between the first interconnects and the second interconnects, the method comprising

• switching resistance states of the variable resistance members from a first state to a second state,
• the switching including:
• applying a first voltage between the plurality of second interconnects and one of the first interconnects for a first time;
• and
• applying a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state, the second voltage having the same polarity as the first voltage and being lower than the first voltage, the second time being longer than the first time.