Asymmetric on-state resistance driver optimized for multi-drop ddr4

An apparatus comprising:

• a first plurality of driver circuits configured to provide a pull up strength of a memory signal that transfers read data across a read line to a memory controller;
• a second plurality of driver circuits configured to provide a pull down strength of said memory signal;
• and
• a plurality of control registers configured to enable one or more of said first plurality of driver circuits and one or more of said second plurality of driver circuits, wherein (a) said pull up strength of said memory signal is configured in response to how many of said first plurality of driver circuits are enabled, (b) said pull down strength of said memory signal is configured in response to how many of said second plurality of driver circuits are enabled and (c) different numbers of said first plurality of driver circuits and said second plurality of driver circuits are enabled to implement an asymmetric voltage swing of said memory signal about an internally generated reference voltage.