Dynamic Random Access Memory For Communications Systems

Abstract

An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, and DRAM cells. A first portion of the DRAM cells may be refreshed by the memory refresh circuit. The DRAM cells store data received via a communication link and a rate at which the first portion of the DRAM cells is refreshed may be adjusted based on a symbol rate at which the data is received via the communication link. The DRAM cells may include one-transistor (“1T”) cells. The adjustment of the rate at which the first portion of the DRAM cells is refreshed may include an enabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a first time interval and a disabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a second time interval.

Dependencies are inferred from the claim text.