Memory device and semiconductor device

A semiconductor device comprising:

• a circuit portion;
• and
• a cell array comprising:
• a plurality of cells;
• a plurality of first wirings;
• and
• a plurality of second wirings,
• wherein one of the plurality of cells comprises a transistor,
• wherein one of the plurality of first wirings is electrically connected to a gate of the transistor,
• wherein one of the plurality of second wirings is electrically connected to one of a source and a drain of the transistor,
• wherein the cell array comprises a region overlapping with the circuit portion,
• wherein the one of the plurality of first wirings is electrically connected to the circuit portion through one of a plurality of first contact holes,
• wherein the one of the plurality of second wirings is electrically connected to the circuit portion through one of a plurality of second contact holes,
• wherein the one of the plurality of first wirings comprises a region extending along a first direction,
• wherein the one of the plurality of second wirings comprises a region extending along a second direction,
• wherein the second direction crosses the first direction, and
• wherein the plurality of second contact holes are arranged along the first direction.

A semiconductor device comprising:

• a circuit portion;
• and
• a cell array comprising:
• a plurality of cells;
• a plurality of first wirings;
• and
• a plurality of second wirings,
• wherein one of the plurality of cells comprises a transistor,
• wherein one of the plurality of first wirings is electrically connected to a gate of the transistor,
• wherein one of the plurality of second wirings is electrically connected to one of a source and a drain of the transistor,
• wherein the cell array comprises a region overlapping with the circuit portion,
• wherein the one of the plurality of first wirings is electrically connected to the circuit portion through one of a plurality of first contact holes,
• wherein the one of the plurality of second wirings is electrically connected to the circuit portion through one of a plurality of second contact holes,
• wherein the one of the plurality of first wirings comprises a region extending along a first direction,
• wherein the one of the plurality of second wirings comprises a region extending along a second direction,
• wherein the second direction crosses the first direction, and
• wherein the plurality of first contact holes are arranged along the second direction.

A semiconductor device comprising:

• a circuit portion;
• and
• a cell array comprising:
• a first cell comprising a first transistor;
• a second cell comprising a second transistor;
• a first wiring;
• a second wiring;
• and
• a third wiring,
• wherein the first wiring is electrically connected to a gate of the first transistor,
• wherein the first wiring is electrically connected to a gate of the second transistor,
• wherein the second wiring is electrically connected to one of a source and a drain of the first transistor,
• wherein the third wiring is electrically connected to one of a source and a drain of the second transistor,
• wherein the cell array comprises a region overlapping with the circuit portion,
• wherein the first wiring is electrically connected to the circuit portion through a first contact hole,
• wherein the second wiring is electrically connected to the circuit portion through a second contact hole,
• wherein the third wiring is electrically connected to the circuit portion through a third contact hole,
• wherein the first wiring comprises a region extending along a first direction,
• wherein the second wiring comprises a region extending along a second direction,
• wherein the third wiring comprises a region extending along the second direction,
• wherein the second direction crosses the first direction, and
• wherein the second contact hole and the third contact hole are arranged along the first direction.

A semiconductor device comprising:

• a circuit portion;
• and
• a cell array comprising:
• a first cell comprising a first transistor;
• a second cell comprising a second transistor;
• a first wiring;
• a second wiring;
• and
• a third wiring,
• wherein the first wiring is electrically connected to a gate of the first transistor,
• wherein the second wiring is electrically connected to a gate of the second transistor,
• wherein the third wiring is electrically connected to one of a source and a drain of the first transistor,
• wherein the third wiring is electrically connected to one of a source and a drain of the second transistor,
• wherein the cell array comprises a region overlapping with the circuit portion,
• wherein the first wiring is electrically connected to the circuit portion through a first contact hole,
• wherein the second wiring is electrically connected to the circuit portion through a second contact hole,
• wherein the third wiring is electrically connected to the circuit portion through a third contact hole,
• wherein the first wiring comprises a region extending along a first direction,
• wherein the second wiring comprises a region extending along the first direction,
• wherein the third wiring comprises a region extending along a second direction,
• wherein the second direction crosses the first direction, and
• wherein the first contact hole and the second contact hole are arranged along the second direction.