Time tracking circuit for fram
AssigneeTexas Instruments Incorporated
InventorDavid J. Toops
Life of this patent
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Abstract
Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
Claims37
A memory circuit comprising:
- a controller to output a signal to an input of a driver after a predetermined delay;
- a transistor coupled an output of the driver;
- the driver to, in response to receiving the signal, output a first voltage to the transistor;
- the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit, a sum of the transistor delay and the predetermined delay corresponding to a minimum amount of delay;
- and
- a ferroelectric random access memory (FRAM) array, the minimum amount of delay corresponding to a number of bit cell rows in the FRAM array, wherein increasing the number of rows increases the minimum amount of delay, the FRAM array including the bit cell.
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The memory circuit of claim 34, wherein the transistor is structured to output the second voltage to a bit line of the bit cell.
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A method comprising:
- outputting, using a controller, a signal to an input of a driver of a memory circuit after a predetermined delay;
- outputting, using the driver, a first voltage to a transistor, the transistor outputting, in response to the transistor receiving the first voltage, a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit, a sum of the transistor delay and the predetermined delay corresponding to a minimum amount of delay, the minimum amount of delay corresponding to at least one of a number of bit cell rows or a number of bit cell columns in an FRAM array, wherein increasing the at least one of the number of rows or the number or columns increases the minimum delay.
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A memory circuit comprising:
- a controller to output a signal to an input of a driver after a predetermined delay;
- a transistor coupled an output of the driver;
- the driver to, in response to receiving the signal, output a first voltage to the transistor;
- the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit, a sum of the transistor delay and the predetermined delay corresponding to a minimum amount of delay;
- and
- an FRAM array, the minimum amount of delay corresponding to a number of bit cell columns in the FRAM array, wherein increasing the number of columns increases the minimum amount of delay, the FRAM array including the bit cell.
Dependencies are inferred from the claim text.