Memory array power reduction through reduced supply voltage

A system, comprising:

• a memory;
• and
• one or more processors coupled to the memory, each of the one or more processors including:
• a storage array;
• periphery logic coupled to the storage array;
• and
• a voltage regulator circuit coupled to an array power supply and a periphery power supply, wherein the periphery power supply is configured to selectively operate at any of a plurality of periphery operating voltages according to a respective power mode of operation, and wherein one or more of the periphery operating voltages is less than a threshold array operating voltage required by the storage array for read or write access during an active mode of storage array operation;
• wherein the voltage regulator circuit is configured to generate, dependent upon a selected power mode of operation, a regulated array power supply that operates at a voltage that satisfies the threshold array operating voltage and is less than an operating voltage of the array power supply, wherein the regulated array power supply is coupled to at least a portion of the storage array;
• wherein two or more different elements within the storage array require different threshold voltages to operate during the active mode of storage array operation;
• and
• wherein the regulated array power supply is one of a plurality of regulated array power supplies generated by the voltage regulator circuit that are respectively physically connected to the two or more different elements, wherein individual ones of the plurality of regulated array power supplies respectively satisfy corresponding ones of the different threshold voltages.

A method, comprising:

• generating, by a voltage regulator circuit coupled to an array power supply and a periphery power supply, a plurality of regulated array power supplies respectively coupled to two or more different elements of a storage array, wherein the two or more different elements of the storage array require different threshold voltages to operate during an active mode of storage array operation, and wherein:
• the generating is dependent on a selected one of a plurality of power modes of operation;
• and
• the periphery power supply selectively operates at any of a plurality of periphery operating voltages according to a respective one of the plurality of power modes of operation;
• and
• performing, by the storage array, read or write accesses using the plurality of regulated array power supplies during the active mode of storage array operation, wherein:
• one or more of the periphery operating voltages is less than a threshold array operating voltage required by the storage array for read or write access during the active mode of storage array operation;
• and
• each of the regulated array power supplies operates at a voltage that respectively satisfies a corresponding one of the different threshold voltages and is less than an operating voltage of the array power supply.