Stacked dram device and method of manufacture
AssigneeRambus Inc.
InventorThomas Vogelsang
Life of this patent
Estimating the term…
Abstract
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
Claims20
A memory device comprising:
- a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
- first memory core circuitry, and
- first input/output (I/O) circuitry;
- a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
- second memory core circuitry, and
- second I/O circuitry;
- and
- wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
A memory module comprising:
- a substrate;
- and
- multiple memory devices mounted to the substrate, each memory device comprising
- a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
- first memory core circuitry, and
- first input/output (I/O) circuitry;
- a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
- second memory core circuitry, and
- second I/O circuitry;
- and
- wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
A memory device comprising:
- a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
- first memory core circuitry, and
- first input/output (I/O) circuitry;
- a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
- second memory core circuitry, and
- second I/O circuitry;
- and
- wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes means for electrically coupling at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
Dependencies are inferred from the claim text.