Shift Register Unit, Organic Light-Emitting Display Panel And Driving Method

A shift register unit, comprising:

• a node potential controller comprising a first output end and a second output end;
• an output unit, wherein the output unit is configured to output, based on a first control signal from the first output end, and a second control signal outputted by the second output end, a first level signal, or a second level signal;
• and wherein the node potential controller further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitor, a second capacitor and a third capacitor;
• wherein a gate of the first transistor, a gate of the second transistor, a gate of the seventh transistor and a first electrode of the third transistor are electrically connected to a first clock signal control end;
• wherein a first electrode of the first transistor and a first electrode of the seventh transistor are electrically connected to a first input signal end;
• and
• wherein a second electrode of the first transistor is electrically connected to a gate of the third transistor;
• wherein a first electrode of the second transistor being electrically connected a first level signal end, and a second electrode of the second transistor is electrically connected to a gate of the sixth transistor;
• wherein a second electrode of the third transistor is electrically connected to a gate of the fifth transistor and the gate of the sixth transistor;
• wherein a gate of the fourth transistor is electrically connected to a second clock signal control end, a first electrode of the fourth transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the fourth transistor is electrically connected to the first output end;
• wherein a first electrode of the fifth transistor being electrically connected to an end of the second level signal;
• wherein a first electrode of the sixth transistor is electrically connected to an end of the second clock signal control, and a second electrode of the sixth transistor is electrically connected to the second output end;
• wherein a second electrode of the seventh transistor is electrically connected to the first output end;
• wherein a gate of the eighth transistor is electrically connected to the first output end, a first electrode of the eighth transistor is electrically connected to the second level signal end, and a second electrode of the eighth transistor is electrically connected to the second output end;
• wherein two ends of the first capacitor are connected respectively to the second clock signal control end and the first output end;
• wherein two ends of the second capacitor are connected respectively to the gate of the fifth transistor and the second output end;
• and
• wherein two ends of the third capacitor are connected respectively to the first electrode of the fifth transistor and the gate of the third transistor.