Shift register unit, gate driving circuit and display device

A shift register unit, comprising an input terminal, a first output terminal and a second output terminal, and further comprising:

• a shift register module connected between the input terminal and the first output terminal, and configured to delay a phase of a signal from the input terminal under a control of a first clock signal, and output the delayed signal at the first output terminal;
• a first input module connected between the first output terminal and a first node, and configured to set the first node to be at a second voltage level when a second clock signal and the first output terminal are both at a first voltage level;
• a second input module connected between the input terminal and the first node, and configured to set the first node to be at the first voltage level when the first clock signal is at the first voltage level, and apply the signal from the input terminal to the first node when the second clock signal is at the first voltage level;
• and
• an output module connected between the first node, the first output terminal, and the second output terminal, and configured to set the second output terminal to be at the second voltage level when the first output terminal is at the first voltage level, and set the second output terminal to be at the first voltage level when the first node is at the first voltage level,
• wherein a phase of the first clock signal and a phase of the second clock signal are opposite to each other.