Hardware architecture for acceleration of computer vision and imaging processing

An image processing circuit for processing a plurality of image streams, the image processing circuit comprising:

• a plurality of hardware accelerators, each hardware accelerator of the plurality of hardware accelerators having an input and an output;
• a multi-ported memory subsystem configured as a shared circular buffer and comprising an interconnect element configured to enable a stream at an output of any first one of the hardware accelerators to be coupled to an input of any second one of the hardware accelerators;
• a plurality of circular buffer write adapters configured to convert incoming image streams into circular buffer data;
• a plurality of circular buffer read adapters configured to convert circular buffer data into outgoing data streams;
• and
• at least one bus synchronizing data within the circular buffer across the plurality of circular buffer write adapters and the plurality of circular buffer read adapters.

A method, comprising:

• for a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data, one of
• chaining two or more of the image processing hardware accelerators to operate in sequence in a first order for a first use case for the image processing hardware accelerators, and
• setting at least one of the image processing hardware accelerators to operate for a second use case for the image processing hardware accelerators;
• for a multi-port memory shared by the plurality of image processing hardware accelerators and configured to store the image data, configuring a portion of the shared memory allocated to one of the image processing hardware accelerators as a circular buffer based on whether the first use case or the second use case is employed;
• and
• configuring an interconnect coupling the memory to one or more of the image processing hardware accelerators to process accesses of the image data by the image processing hardware accelerators, wherein the interconnect includes a head pointer bus configured to carry a head pointer for the circular buffer and a tail pointer bus configured to carry a tail pointer for the circular buffer.