SYSTEMS AND METHODS FOR MANAGING INTER-CPU INTERRUPTS BETWEEN MULTIPLE CPUs

A computer-readable medium having stored therein a set of instructions, which when executed by a computing device implemented a method for managing inter-processor interrupts via a set of operations, the set of operations comprising:

• writing a target processor identifier and an interrupt number in an interrupt send register of an interrupt sending processor;
• writing the interrupt number in one of a plurality of locations of an interrupt receive register corresponding to a target processor;
• writing an identifier of a location of a highest priority interrupt of a plurality of interrupts received in the interrupt receive register in an interrupt pick register;
• reading the interrupt pick register to determine the highest priority interrupt;
• reading a matrix associated with the target processor to determine a sender of the highest priority interrupt;
• and
• processing the highest priority interrupt.