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US 2017/0255574 A1Published application
Memory interface apparatus
AssigneeElectronics and Telecommunications Research Institute
InventorsYong Seok CHOI, Hyuk Je KWON
Life of this patent
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Abstract
A memory interface apparatus is provided. The apparatus includes a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel interface and a memory-side protocol processor connected to a memory through a parallel interface, and the CPU-side protocol processor and the memory-side protocol processor are connected through a serial link.
Claims13
A memory interface apparatus comprising:
- a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel interface;
- and
- a memory-side protocol processor connected to a memory through a parallel interface,
- wherein the CPU-side protocol processor and the memory-side protocol processor are connected through a serial link.
1 more element
Dependencies are inferred from the claim text.