Atomic instruction having a local scope limited to an intermediate cache level

A multi-core processor comprising:

• a cache memory shared by a group of several cores configured to delegate atomic instructions to the cache memory;
• in its instruction set, an atomic read-modify-write instruction, taking as a parameter a memory address of a shared variable, wherein the atomic instruction can have a global scope;
• a cache memory controller configured for receiving and processing each global atomic instruction executed by a given core of the group by globally locking an address space containing the address of the shared variable, to prevent access to the shared variable by any other core during execution of the global atomic instruction;
• wherein the atomic instruction can also have a local scope, the cache memory controller being configured for processing each local atomic instruction executed by a given core of the group by locally locking a cache line allocated to the address of the shared variable, while authorizing access to the shared variable to cores connected to another cache memory of same level during execution of the local atomic instruction.