Control of persistent memory via a computer bus

A memory device, comprising:

• a target memory, having a memory address space;
• a volatile buffer memory, which is coupled to receive data written over a bus in transaction packets to the memory device for storage in specified addresses within the memory address space, each transaction packet comprising a transaction descriptor, which comprises a flush flag;
• and
• a memory controller, which is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush to the target memory the data held in the buffer memory for which the flush flag was set in the transaction packets that conveyed the data to the memory device.

A method for data storage in a memory device that includes a target memory and a volatile buffer memory, the method comprising:

• receiving in the volatile buffer memory data written over a bus to the memory device for storage in specified addresses within a memory address space of the memory device;
• receiving, via the bus, a flush instruction;
• and
• in response to the flush instruction, immediately flushing the data held in the buffer memory with specified addresses within the memory address space to the target memory.

A method for data storage in a memory device that includes a target memory and a volatile buffer memory, the method comprising:

• receiving in the volatile buffer memory data written over a bus in transaction packets to the memory device for storage in specified addresses within a memory address space of the memory device, each transaction packet comprising a transaction descriptor, which comprises a flush flag;
• and
• receiving, via the bus, a flush instruction;
• and
• in response to the flush instruction, immediately flushing to the target memory the data held in the buffer memory for which the flush flag was set in the transaction packets that conveyed the data to the memory device.