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US 2017/0255558 A1Published application
Isolation mode in a cache coherent system
AssigneeArteris, Inc.
InventorsCraig Stephen Forrest, David A. Kruckemyer
Life of this patent
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Abstract
The invention involves isolating a cache coherence controller from agents or units. The term unit as used herein may refer to one or more circuits, components, registers, processors, software subroutines, or any combination thereof. The separate units communicate with each other and are logically coupled.
Claims3
A system-on-chip (SoC) with cache coherence, the SoC comprising:
- a plurality of units, each including an agent interface, distributed within the SoC's floorplan;
- coherent memory, including a cache coherent controller, in communication with each of the plurality of units;
- and
- non-coherent memory in communication with each of the plurality of units,
- wherein a first plurality of units, using the agent interface of each of the first plurality of units, are isolated from the cache coherent controller, such that when the cache coherent controller is isolated from the first plurality of units there no communication between the cache coherent controller and the cache coherent controller communicates with a second plurality of units to at least reduce power consumption,
- wherein the first plurality of units and the second plurality of units collectively represent all of the plurality of units.
3 more elements
A method of reducing power consumption in system-on-chip (SoC) with cache coherence, the method comprising:
- distributing a plurality of units, each including an agent interface, within a floorplan of the SoC;
- communicating between a coherent memory, including a cache coherent controller, and each of the plurality of units;
- communicating between non-coherent memory and each of the plurality of units;
- isolating a first plurality of units from the cache coherent controller and allowing communication between a second plurality of units and the cache coherent controller,
- wherein the first plurality of units and the second plurality of units collectively represent all of the plurality of units.
2 more elements
A system comprising:
- a plurality of agents, each including an agent interface, distributed within the system;
- coherent memory, including a cache coherent controller, the coherent memory being in communication with each of the plurality of agents through the cache coherent controller;
- and
- non-coherent memory in communication with each of the plurality of agents through the agent interface of each of the plurality of agents,
- wherein the coherent memory communicates with a second plurality of agents,
- wherein at least one agent, using the agent interface of the at least one agent, is isolated from the coherent memory, such that when the coherent memory is isolated from the at least one agent there no communication between the cache coherent controller and the at agent interface of the least one agent thereby at least reducing the system's power consumption,
- wherein the at least one agent and the second plurality of agents collectively represent all of the plurality of agents.
4 more elements
Dependencies are inferred from the claim text.