Systems and methods for dynamic random access memory (dram) sub-channels

A system, comprising:

• a memory controller;
• and
• a dynamic random access memory (DRAM) coupled to the memory controller, the DRAM comprising:
• control logic for generating row addresses and a column addresses;
• a first bank that is coupled to the control logic, the first bank comprising:
• a first subarray including a first storage unit coupled to a first row-buffer in a first sub-channel and a second storage unit in a second sub-channel, wherein the first subarray is associated with a first row address and the first sub-channel is associated with a first column address that is stored in the first sub-channel and used to select a first portion of data from the first row-buffer for output to a data bus;
• a second subarray including a third storage unit in the first sub-channel and a fourth storage unit coupled to a second row-buffer in the second sub-channel, wherein the second subarray is associated with a second row address and the second sub-channel is associated with a second column address that is stored in the second sub-channel and used to select a second portion of data from the second row-buffer for output to the data bus;
• and
• a second bank that is coupled to the control logic.

A method for accessing a dynamic random access memory (DRAM), comprising:

• generating row addresses and column addresses for a first bank of multiple banks within the DRAM;
• providing a first row address to a first subarray comprising a first storage unit and a second storage unit;
• providing a second row address to a second subarray comprising a third storage unit and a fourth storage unit;
• providing a first column address to a first sub-channel, the first sub-channel comprising the first storage unit coupled to a first row-buffer and the third storage unit;
• storing the first column address in the first sub-channel;
• providing a second column address to a second sub-channel, the second sub-channel comprising the second storage unit and a fourth subarray including the fourth storage unit coupled to a second row-buffer;
• storing the second column address in the second sub-channel;
• selecting, based on the first column address, a first portion of data from the first row-buffer for output to a data bus;
• and
• selecting, based on the second column address, a second portion of data from the second row-buffer for output to the data bus.