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US 2017/0255531 A1Published application
Single and double chip spare
AssigneeHewlett Packard Enterprise Development LP
InventorsGary Gostin, Erin A. Handgen
Life of this patent
Estimating the term…
Abstract
Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
Claims14
A device comprising:
- a memory controller to:
- access a first portion of a memory, the first portion of the memory operating in single chip spare mode;
- and
- access a second portion of the memory, the second portion of the memory operating in double chip spare mode.
1 more element
A method comprising:
- detecting a single chip error in a first region of memory, the first region of memory operating in single chip spare mode;
- selecting a second region of memory equal in size to the first region of memory, the second region of memory operating in single chip spare mode;
- and
- converting the first and second region of memory from single chip spare mode to double chip spare mode.
1 more element
A method comprising:
- detecting an error in a portion of a memory operating in single chip spare mode;
- determining a first region of the memory that is affected by the error;
- and
- converting the first region to operate in double chip spare mode.
1 more element
The method of claim 12 wherein converting the first region further comprises:
- determining a second region of the memory equal in size to the first region, the second region containing no errors and operating in the single chip spare mode;
- calculating a double chip spare error correction code for each cache line the first and second regions;
- storing each cache line and calculated error correction code in a combined region comprising the first and second regions. 14 The method of claim 13 further comprising:
- detecting a second single chip error in the combined region, the second error occurring in the second region;
- converting the combined region back into the first memory region and the second memory region, wherein the first and second regions operate in the single chip spare mode;
- determining a third region of the memory equal in size to the first region, the third region containing no errors and operating in the single chip spare mode;
- calculating a double chip spare error correction code for each cache line in the first and third regions;
- storing each cache line and calculated error correction code in a combined region comprising the first and third regions.
5 more elements
The method of claim 14 further comprising:
- determining a fourth region of the memory equal in size to the second region, the fourth region containing no errors and operating in the single chip spare mode;
- calculating a double chip spare error correction code for each cache line in the second and fourth regions;
- storing each cache line and calculated error correction code in a combined region comprising the second and fourth regions.
Dependencies are inferred from the claim text.